Silicon Labs /EFR32ZG23B010F512IM48 /RAC_S /CTRL

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Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FORCEDISABLE)FORCEDISABLE 0 (PRSTXEN)PRSTXEN 0 (X0)TXAFTERRX 0 (DIRECT)PRSMODE 0 (RXSEARCH)PRSCLR 0 (X0)TXPOSTPONE 0 (X0)ACTIVEPOL 0 (X0)PAENPOL 0 (X0)LNAENPOL 0 (X0)PRSRXDIS 0 (X0)PRSFORCETX 0 (SEQRESET)SEQRESET 0 (EXITSHUTDOWNDIS)EXITSHUTDOWNDIS 0 (CPUWAITDIS)CPUWAITDIS 0 (SEQCLKDIS)SEQCLKDIS 0 (RXOFDIS)RXOFDIS

PRSFORCETX=X0, TXAFTERRX=X0, ACTIVEPOL=X0, PRSRXDIS=X0, LNAENPOL=X0, TXPOSTPONE=X0, PRSCLR=RXSEARCH, PRSMODE=DIRECT, PAENPOL=X0

Description

No Description

Fields

FORCEDISABLE

Force Radio Disable

PRSTXEN

PRS TX Enable

TXAFTERRX

TX After RX

0 (X0): TX will not be started automatically.

1 (X1): A transition to TX is automatically started when a received frame is accepted by the FRC.

PRSMODE

PRS RXEN Mode

0 (DIRECT): The PRS signal is used directly

1 (PULSE): The PRS signal is used as an RX enable pulse

PRSCLR

PRS RXEN Clear

0 (RXSEARCH): The PRS RXEN signal is cleared when the RSM state enters RXSEARCH

1 (PRSCH): The Selected PRS channel in PRSCLRSEL is used as a disable pulse

TXPOSTPONE

TX Postpone

0 (X0): In the TX state transmit data is output.

1 (X1): In the TX state an unmodulated carrier is output until this bit is cleared.

ACTIVEPOL

ACTIVE signal polarity

0 (X0): Active low

1 (X1): Active high

PAENPOL

PAEN signal polarity

0 (X0): Active low

1 (X1): Active high

LNAENPOL

LNAEN signal polarity

0 (X0): Active low

1 (X1): Active high

PRSRXDIS

PRS RX Disable

0 (X0): PRS will not disable RX

1 (X1): The channel selected by PRSRXDISSEL will generate a disable RX pulse

PRSFORCETX

PRS Force RX

0 (X0): PRS will not force TX

1 (X1): The channel selected by PRSFORCETXSEL will generate a force TX pulse

SEQRESET

SEQ reset

EXITSHUTDOWNDIS

Exit SHUTDOWN state Disable

CPUWAITDIS

SEQ CPU Wait Disable

SEQCLKDIS

SEQ Clk Disable

RXOFDIS

Switch to RXOVERFLOW Disable

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